The present invention relates to the manufacture of semiconductor integrated circuits. More particularly, the invention is illustrated with regard to memory cell structures for a flash memory cell or flash E2PROM or EPROM cell, but it will be recognized that the invention has a wider range of applicability. Merely by way of example, the present invention can be applied to a variety of embedded memory cell structures such as microprocessors (xe2x80x9cMICROsxe2x80x9d), microcontrollers, application specific integrated circuits (xe2x80x9cASICsxe2x80x9d), and the like.
A variety of memory devices have been proposed or used in industry. An example of such a memory device is an erasable programmable read-only memory (xe2x80x9cEPROMxe2x80x9d) device. The EPROM device is both readable and erasable, i.e., programmable. In particular, an EPROM is implemented using a floating gate field effect transistor, which has binary states. That is, a binary state is represented by the presence or absence of charge on the floating gate. The charge is generally sufficient to prevent conduction even when a normal high signal is applied to the gate of the EPROM transistor.
Numerous varieties of EPROMs are available. In the traditional and most basic form, EPROMs are programmed electrically and erased by exposure to ultraviolet light. These EPROMs are commonly referred to as ultraviolet erasable programmable read-only memories (xe2x80x9cUVEPROMxe2x80x9ds). UVEPROMs can be programmed by running a high current between a drain and a source of the UVEPROM transistor while applying a positive potential to the gate. The positive potential on the gate attracts energetic (i.e., hot) electrons from the drain-to-source current, where the electrons jump or inject into the floating gate and become trapped on the floating gate.
Another form of EPROM is the electrically erasable programmable read-only memory (xe2x80x9cEEPROMxe2x80x9d or xe2x80x9cE2PROMxe2x80x9d). EEPROMs are often programmed and erased electrically by way of a phenomenon known as Fowler-Nordheim tunneling. Still another form of EPROM is a xe2x80x9cFlash EPROM,xe2x80x9d which is programmed using hot electrons and erased using the Fowler-Nordheim tunneling phenomenon. Flash EPROMs can be erased in a xe2x80x9cflashxe2x80x9d or bulk mode in which all cells in an array or a portion of an array can be erased simultaneously using Fowler-Nordheim tunneling, and are commonly called xe2x80x9cFlash cellsxe2x80x9d or xe2x80x9cFlash devices.xe2x80x9d
A limitation with the flash memory cell is that high voltage is often required to program the device. In some conventional devices, the high voltage can be up to double the amount of voltage needed to operate the device. As device size becomes smaller, high voltage is often detrimental to the operation of the device, as well as its reliability. In particular, high voltages often require a high voltage supply, which uses a more efficient voltage pump. This voltage pump generally requires a thicker oxide for the transistor device, which is often more difficult to make accurately. Additionally, higher voltages often lead to reliability and quality problems. These and other limitations exist in conventional flash memory devices. From the above it is seen that a flash memory cell structure that is easy to fabricate, cost effective, and reliable is often desired.
The present invention provides a technique, including a method and device, for an improved floating gate structure of a flash memory cell in an integrated circuit device. This improved floating gate structure is provided with a higher surface area that is capacitively coupled to a control gate by way of an undercut gate structure. The undercut gate structure provides a higher gate coupling ratio, which is a desirable result.
In a specific embodiment, the present invention provides a method of fabricating an integrated circuit device such as a flash memory device and resulting cell. The method includes a step of providing a substrate, which has an active region over which lies a thin layer of dielectric material, which is commonly termed a xe2x80x9ctunnel oxidexe2x80x9d layer, but is not limited to such a layer or material. The method uses a step of forming a floating gate layer overlying the thin layer of dielectric material. The floating gate layer has novel geometric features including undercut edges, also called slant edges, which are made by way of plasma etching techniques, which would generally be considered undesirable using conventional process structures. The slant edges extend from an upper surface of the floating gate layer to the dielectric material, where the upper surface is much larger in surface area than the surface area overlying the tunnel oxide layer. That is, the slant edges create a smaller xe2x80x9cfootprintxe2x80x9d overlying the tunnel oxide layer relative to the region of the floating gate which is capacitively coupled to a control gate layer. By way of the smaller footprint, the device has desirable characteristics.
In an alternative embodiment, the present invention provides a novel semiconductor device structure for a flash memory cell. The memory cell includes a variety of features such as a substrate, which has an active region over which lies a layer of dielectric material. This dielectric layer is termed the tunnel oxide layer, but is not limited to this material. A floating gate layer is formed overlying the tunnel oxide layer in the active region. The floating gate layer has slant edges that extend to the dielectric material. The slant edges can be made using a variety of techniques including plasma etching, which may have anisotropic and isotropic characteristics. The slant edges create a smaller geometric area for the tunnel oxide region relative to the area between the floating gate layer and the control gate layer, thereby providing some desirable device features.
Numerous benefits are achieved in one or more embodiments of the present invention over previous existing techniques. For example, the present invention provides a relatively simple structure to increase a gate coupling ratio (xe2x80x9cGCRxe2x80x9d) of a flash memory device. The increased gate coupling ratio leads to lower voltages needed to program the device. Additionally, the present invention uses a simple technique for manufacturing the novel flash memory cell. This technique relies on conventional technology, which was generally undesirable in the manufacture of integrated circuits. These and other benefits are described throughout the present specification, and more particularly below.
The present invention achieves these benefits in the context of known process technology. A further understanding of the nature and advantages of the present invention, however, may be realized by reference to the latter portions of the specification and attached drawings.